COMISS

Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS

Opcodes

Hex	Mnemonic	Encoding	Long Mode	Legacy Mode	Description
0F 2F /r	COMISS xmm1, xmm2/m32	A	Valid	Valid	Compare low singleprecision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.

Instruction Operand Encoding

Op/En	Operand 0	Operand 1	Operand 2	Operand 3
A	NA	NA	ModRM:r/m (r)	ModRM:reg (r)

Description

Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).

Operand 1 is an XMM register; Operand 2 can be an XMM register or a 32 bit memory location.

The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid numeric exception only if a source operand is an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

RESULT = OrderedCompare(SRC1[31:0] <> SRC2[31:0]) {
(* Set EFLAGS *)
CASE (RESULT) OF UNORDERED: ZF, PF, CF = 111;
	GREATER_THAN: ZF, PF, CF = 000;
	LESS_THAN: ZF, PF, CF = 001;
	EQUAL: ZF, PF, CF = 100;
ESAC;
OF, AF, SF = 0;
}

Exceptions

SIMD Floating-Point Exceptions

Invalid (if SNaN or QNaN operands), Denormal.

64-Bit Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#PF(fault-code)	For a page fault.
#GP(0)	If the memory address is in a non-canonical form.
#SS(0)	If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code)	For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception	Description
#UD	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#GP	If any part of the operand lies outside the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD	If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#PF(fault-code)	For a page fault.
#SS(0)	For an illegal address in the SS segment.
#GP(0)	For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.