CVTSD2SS
Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value
Opcodes
| Hex | Mnemonic | Encoding | Long Mode | Legacy Mode | Description |
|---|---|---|---|---|---|
| F2 0F 5A /r | CVTSD2SS xmm1, xmm2/m64 | A | Valid | Valid | Convert one doubleprecision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1. |
Instruction Operand Encoding
| Op/En | Operand 0 | Operand 1 | Operand 2 | Operand 3 |
|---|---|---|---|---|
| A | NA | NA | ModRM:r/m (r) | ModRM:reg (w) |
Description
Converts a double-precision floating-point value in the source operand (second operand) to a single-precision floating-point value in the destination operand (first operand).
The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register. The result is stored in the low doubleword of the destination operand, and the upper 3 doublewords are left unchanged. When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Pseudo Code
DEST[31:0] = Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]); (* DEST[127:32] unchanged *)
Exceptions
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
64-Bit Mode Exceptions
| Exception | Description |
|---|---|
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
| #XM | If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1. |
| #NM | If CR0.TS[bit 3] = 1. |
| #PF(fault-code) | For a page fault. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #SS(0) | If a memory address referencing the SS segment is in a non- canonical form. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
| Exception | Description |
|---|---|
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #PF(fault-code) | For a page fault. |
| Same exceptions as in real address mode. | |
Real-Address Mode Exceptions
| Exception | Description |
|---|---|
| #UD | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
| #XM | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. |
| #NM | If CR0.TS[bit 3] = 1. |
| #GP | If any part of the operand lies outside the effective address space from 0 to FFFFH. |
Protected Mode Exceptions
| Exception | Description |
|---|---|
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
| #XM | If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1. |
| #NM | If CR0.TS[bit 3] = 1. |
| #PF(fault-code) | For a page fault. |
| #SS(0) | For an illegal address in the SS segment. |
| #GP(0) | For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. |