Return Maximum Packed Double-Precision Floating-Point Values
Hex | Mnemonic | Encoding | Long Mode | Legacy Mode | Description |
---|---|---|---|---|---|
66 0F 5F /r | MAXPD xmm1, xmm2/m128 | A | Valid | Valid | Return the maximum double-precision floating-point values between xmm2/m128 and xmm1. |
Op/En | Operand 0 | Operand 1 | Operand 2 | Operand 3 |
---|---|---|---|---|
A | NA | NA | ModRM:r/m (r) | ModRM:reg (r, w) |
Performs a SIMD compare of the packed double-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the maximum value for each pair of values to the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is forwarded unchanged to the destination (that is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
DEST[63:0] = IF ((DEST[63:0] = 0.0) and (SRC[63:0] = 0.0)) SRC[63:0]; ELSE IF (DEST[63:0] = SNaN) SRC[63:0]; ELSE IF (SRC[63:0] = SNaN) SRC[63:0]; ELSE IF (DEST[63:0] > SRC[63:0]) DEST[63:0]; ELSE SRC[63:0]; FI; FI; FI; FI; DEST[127:64] = IF ((DEST[127:64] = 0.0) and (SRC[127:64] = 0.0)) SRC[127:64]; ELSE IF (DEST[127:64] = SNaN) SRC[127:64]; ELSE IF (SRC[127:64] = SNaN) SRC[127:64]; ELSE IF (DEST[127:64] > SRC[63:0]) DEST[127:64]; ELSE SRC[127:64]; FI; FI; FI; FI;
Invalid (including QNaN source operand), Denormal.
Exception | Description |
---|---|
#UD | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
#XM | If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1. |
#NM | If CR0.TS[bit 3] = 1. |
#PF(fault-code) | For a page fault. |
#GP(0) | If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. |
#SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
Same exceptions as in protected mode.
Exception | Description |
---|---|
#PF(fault-code) | For a page fault. |
Same exceptions as in real address mode. |
Exception | Description |
---|---|
#UD | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
#XM | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. |
#NM | If CR0.TS[bit 3] = 1. |
#GP | If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. |
Exception | Description |
---|---|
#UD | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
#XM | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. |
#NM | If CR0.TS[bit 3] = 1. |
#PF(fault-code) | For a page fault. |
#SS(0) | If a memory operand effective address is outside the SS segment limit. |
#GP(0) | For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. |