MINSD

Return Minimum Scalar Double-Precision Floating-Point Value

Opcodes

Hex	Mnemonic	Encoding	Long Mode	Legacy Mode	Description
F2 0F 5D /r	MINSD xmm1, xmm2/m64	A	Valid	Valid	Return the minimum scalar double-precision floating-point value between xmm2/mem64 and xmm1.

Instruction Operand Encoding

Op/En	Operand 0	Operand 1	Operand 2	Operand 3
A	NA	NA	ModRM:r/m (r)	ModRM:reg (r, w)

Description

Compares the low double-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the minimum value to the low quadword of the destination operand. The source operand can be an XMM register or a 64-bit memory location. The destination operand is an XMM register. When the source operand is a memory operand, only the 64 bits are accessed. The high quadword of the destination operand remains unchanged.

If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned).

If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

DEST[63:0] =
IF ((DEST[63:0] = 0.0) and (SRC[63:0] = 0.0))
	SRC[63:0];
ELSE
	IF (DEST[63:0] = SNaN)
		SRC[63:0];
	ELSE
		IF (SRC[63:0] = SNaN)
			SRC[63:0];
		ELSE
			IF (DEST[63:0] < SRC[63:0])
				DEST[63:0];
			ELSE
				SRC[63:0];
			FI;
		FI;
	FI;
FI;
(* DEST[127:64] is unchanged *);

Exceptions

SIMD Floating-Point Exceptions

Invalid (including QNaN source operand), Denormal.

64-Bit Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#PF(fault-code)	For a page fault.
#GP(0)	If the memory address is in a non-canonical form.
#SS(0)	If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code)	For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception	Description
#UD	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#GP	If any part of the operand lies outside the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception	Description
#AC(0)	If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD	If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#XM	If an unmasked SIMD floating-point exception and CR4.OSXM MEXCPT[bit 10] = 1.
#NM	If CR0.TS[bit 3] = 1.
#PF(fault-code)	For a page fault.
#SS(0)	If a memory operand effective address is outside the SS segment limit.
#GP(0)	For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.