MOVNTPS
Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
Opcodes
| Hex | Mnemonic | Encoding | Long Mode | Legacy Mode | Description |
|---|---|---|---|---|---|
| 0F 2B /r | MOVNTPS m128, xmm | A | Valid | Valid | Move packed single-precision floating-point values from xmm to m128 using non-temporal hint. |
Instruction Operand Encoding
| Op/En | Operand 0 | Operand 1 | Operand 2 | Operand 3 |
|---|---|---|---|---|
| A | NA | NA | ModRM:reg (r) | ModRM:r/m (w) |
Description
Moves the double quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is an XMM register, which is assumed to contain four packed single-precision floating-point values. The destination operand is a 128-bit memory location.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see "Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in theIntel®64 and IA-32 Architectures Software Developer's Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPS instructions if multiple processors might use different memory types to read/write the destination memory locations.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Pseudo Code
DEST = SRC;
Exceptions
SIMD Floating-Point Exceptions
None.
64-Bit Mode Exceptions
| Exception | Description |
|---|---|
| #UD | If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. |
| #NM | If CR0.TS[bit 3] = 1. |
| #PF(fault-code) | For a page fault. |
| #GP(0) | If the memory address is in a non-canonical form. INSTRUCTION SET REFERENCE, A-M If memory operand is not aligned on a 16-byte boundary, regardless of segment. |
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
| Exception | Description |
|---|---|
| #PF(fault-code) | For a page fault. |
| Same exceptions as in real address mode. | |
Real-Address Mode Exceptions
| Exception | Description |
|---|---|
| #UD | If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used. |
| #NM | If CR0.TS[bit 3] = 1. |
| #GP | If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. |
Protected Mode Exceptions
| Exception | Description |
|---|---|
| #UD | If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If the LOCK prefix is used. |
| #NM | If CR0.TS[bit 3] = 1. |
| #PF(fault-code) | For a page fault. |
| #SS(0) | For an illegal address in the SS segment. |
| #GP(0) | For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. |