|Hex||Mnemonic||Encoding||Long Mode||Legacy Mode||Description|
|0F 01 C9||MWAIT||A||Valid||Valid||A hint that allow the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events.|
|Op/En||Operand 0||Operand 1||Operand 2||Operand 3|
MWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state. There are two principal targeted usages: address-range monitor and advanced power management. Both usages of MWAIT require the use of the MONITOR instruction.
A CPUID feature flag (ECX bit 3; CPUID executed EAX = 1) indicates the availability of MONITOR and MWAIT in the processor. When set, MWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLES MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an illegal opcode exception.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
For address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions allow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized operation to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or a store operation to the address range armed by MONITOR.
ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized state the processor should enter.
For Pentium 4 processors (CPUID signature family 15 and model 3), non-zero values for EAX and ECX are reserved. Later processors defined ECX=1 as a valid extension (see below).
The following cause the processor to exit the implementation-dependent-optimized state: a store to the address range armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause the processor to exit the implementation-dependent-optimized state.
In addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state if either (1) the interrupt would be delivered to software (e.g., if HLT had been executed instead of MWAIT); or (2) ECX = 1. Implementation-specific conditions may result in an interrupt causing the processor to exit the implementation-dependent-optimized state even if interrupts are masked and ECX = 0.
Following exit from the implementation-dependent-optimized state, control passes to the instruction following the MWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before execution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the MWAIT instruction following the handling of an SMI.
If the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has not been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-optimized state. Execution will resume at the instruction following the MWAIT.
MWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while waiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions for power management is indicated by CPUID.05H.ECX reporting 1.
EAX and ECX will be used to communicate the additional information to the MWAIT instruction, such as the kind of optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions may cause a processor to ignore the hint and enter a different optimized state. Future processor implementations may implement several optimized "waiting" states and will select among those states based on the hint argument.
Table 3-62 describes the meaning of ECX and EAX registers for MWAIT extensions.
|0||Treat masked interrupts as break events (e.g., if EFLAGS.IF=0). May be set only if CPUID.01H:ECX.MONITOR[bit 3] = 1.|
|3 : 0||Sub C-state witdin a C-state, indicated by bits [7:4]|
|7 : 4||
Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states
Note that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address range armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by other processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such cases.
For additional details of MWAIT extensions, see Chapter 14, "Power and ThermalManagement," ofIntel® 64 and IA-32 Architectures Software Developer's Manual,Volume 3A.
(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument inECX as an instruction extension MWAIT EAX, ECX *) WHILE (("Monitor Hardware is in armed state")) implementation_dependent_optimized_state(EAX, ECX); ELIHW; Set the state of Monitor Hardware as triggered;
|#UD||If the current privilege level is not 0. If CPUID.01H:ECX.MONITOR[bit 3] = 0.|
|#GP(0)||If RCX[63:1] != 0. If RCX = 1 and CPUID.05H:ECX[bit 3] = 0.|
Same exceptions as in protected mode.
|#UD||The MWAIT instruction is not recognized in virtual-8086 mode (even if CPUID.01H:ECX.MONITOR[bit 3] = 1).|
|#UD||If CPUID.01H:ECX.MONITOR[bit 3] = 0.|
|#GP||If ECX[31:1] != 0. If ECX = 1 and CPUID.05H:ECX[bit 3] = 0.|
|#UD||If CPUID.01H:ECX.MONITOR[bit 3] = 0. If current privilege level is not 0.|
|#GP(0)||If ECX[31:1] != 0. If ECX = 1 and CPUID.05H:ECX[bit 3] = 0.|