PMINUB

Minimum of Packed Unsigned Byte Integers

Opcodes

Hex	Mnemonic	Encoding	Long Mode	Legacy Mode	Description
66 0F DA /r	PMINUB xmm1, xmm2/m128	A	Valid	Valid	Compare unsigned byte integers in xmm2/m128 and xmm1 and returns minimum values.
0F DA /r	PMINUB mm1, mm2/m64	A	Valid	Valid	Compare unsigned byte integers in mm2/m64 and mm1 and returns minimum values.

Instruction Operand Encoding

Op/En	Operand 0	Operand 1	Operand 2	Operand 3
A	NA	NA	ModRM:r/m (r)	ModRM:reg (r, w)

Description

Performs a SIMD compare of the packed unsigned byte integers in the destination operand (first operand) and the source operand (second operand), and returns the minimum value for each pair of byte integers to the destination operand. The source operand can be an MMX technology register or a 64-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Pseudo Code

(* PMINUB instruction for 64-bit operands: *)
IF DEST[7:0] < SRC[17:0]
	DEST[7:0] = DEST[7:0];
ELSE
	DEST[7:0] = SRC[7:0];
FI;
(* Repeat operation for 2nd through 7th bytes in source and destination operands *)
IF DEST[63:56] < SRC[63:56]
	DEST[63:56] = DEST[63:56];
ELSE
	DEST[63:56] = SRC[63:56];
FI;
(* PMINUB instruction for 128-bit operands: *)
IF DEST[7:0] < SRC[17:0]
	DEST[7:0] = DEST[7:0];
ELSE
	DEST[7:0] = SRC[7:0];
FI; (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
IF DEST[127:120] < SRC[127:120]
	DEST[127:120] = DEST[127:120];
ELSE
	DEST[127:120] = SRC[127:120];
FI;

Flags Affected

None. Numeric Exceptions None.

Exceptions

Numeric Exceptions

None.

64-Bit Mode Exceptions

Exception	Description
#AC(0)	(64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code)	If a page fault occurs.
#MF	(64-bit operations only) If there is a pending x87 FPU exception.
#NM	If CR0.TS[bit 3] = 1.
#UD	If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. If the LOCK prefix is used.
#GP(0)	If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment.
#SS(0)	If a memory address referencing the SS segment is in a non-canonical form.

Compatibility Mode Exceptions

Same as for protected mode exceptions.

Virtual-8086 Mode Exceptions

Exception	Description
#AC(0)	(64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
#PF(fault-code)	For a page fault.
Same exceptions as in real address mode.

Real-Address Mode Exceptions

Exception	Description
#MF	(64-bit operations only) If there is a pending x87 FPU exception.
#NM	If CR0.TS[bit 3] = 1.
#UD	If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#GP	(128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

Protected Mode Exceptions

Exception	Description
#AC(0)	(64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#PF(fault-code)	If a page fault occurs.
#MF	(64-bit operations only) If there is a pending x87 FPU exception.
#NM	If CR0.TS[bit 3] = 1.
#UD	If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. If the LOCK prefix is used.
#SS(0)	If a memory operand effective address is outside the SS segment limit.
#GP(0)	If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.